Electronic circuit designers use electronic design automation (EDA) tools, a category of computer aided design (CAD) tools, to create representations of the cells in a particular circuit and the conductors (called “interconnects” or “nets”) that couple the cells together. EDA tools allow designers to construct a circuit design, generate a layout and simulate its performance using a computer and without requiring the costly and lengthy process of fabrication. EDA tools are indispensable for designing modern, very-large-scale integrated circuits (VSLICs).
Timing is a major concern in all IC designs, because circuits will not operate properly unless signals can propagate properly through them. Consequently, “timing signoff” is a required step in the designing of a circuit, particularly an IC, that takes place after layout of the IC. Timing signoff involves using one type of EDA tool, a signoff analysis tool, to determine the time that signals will take to propagate through the circuit. “Setup” violations occur if signal propagation speeds are too slow. “Hold” violations occur if signal propagation speeds are too fast. Signal propagations speeds are particularly important in critical paths. For this reason, substantial effort is often expended to resolve setup and hold violations in the critical paths of an IC design. This is done during timing signoff by adjusting the speed of the cells in the critical paths.
Cells are made larger to increase the speed of a critical path that produces setup violations, and delay cells are added to decrease the speed of a critical path that produces hold violations. Unfortunately, both of these adjustments increase the size (area) and power dissipation of a path. Since a modern IC has thousands, and perhaps millions, of paths that may require adjustment, the combined effect on size and power requirements can be substantial and mean the difference between an IC that is commercially viable and one that is not.